A DRAM such as an SDRAM (Synchronous Dynamic Random-Access Memory) stores information by charge retention using a capacitor structure. With charge retention, charge is lost gradually owing to a miniscule leakage current. This necessitates an operation, namely a so-called refresh operation, in which information is read out and the same information written in before charge is lost. Two types of refresh operations, namely auto-refresh and self-refresh, are available for use in an SDRAM. These two types of refresh operations differ in terms of method of control at end of the refresh operation.
With self-refresh, the device itself generates a periodic signal to achieve refresh without relying upon an external clock. In self-refresh, as illustrated in FIG. 21A, if a self-refresh entry signal (SELF REF ENTRY) is input externally, refresh is performed by generating a refresh signal (REF) at a certain fixed period. Refresh of sequential addresses is repeated until a self-refresh exit signal (SELF REF EXIT) arrives from outside.
With auto-refresh, on the other hand, refresh of word lines necessary for a single refresh starts in response to receipt of an external refresh command and refresh is terminated automatically. According to auto-refresh, as illustrated in FIG. 21B, auto-refresh is performed only in an auto-refresh period of time (tRFC in FIG. 23) merely in response to entry of an auto-refresh command (AUTO REF COM) from the outside, and auto-refresh ends automatically.
An SDRAM has a DLL circuit for aligning the phases of a system clock (external clock), which is input externally, and an internal clock, and the DLL is allowed to continue operating when the device is active and also in the auto-refresh period. Although the DLL circuit is a circuit for synchronizing the output data and the external clock, the SDRAM does not output data and does not require a DLL operation in the standby state. It is preferred, therefore, that the DLL circuit be powered down in order to reduce consumption of current. However, if the standby state lasts for too long, there is an increase in jitter owing to phase mismatch between the external and internal clocks ascribable to a change in ambient temperature, etc. Accordingly, it is arranged to prevent an increase in jitter by causing the DLL circuit to operate at the time of auto-refresh by utilizing an auto-refresh command that always arrives at a prescribed cycle, e.g., every 7.8 μs. Further, since a row-active signal RAS (see FIG. 22) becomes active both when the device is active and in the auto-refresh period, it is arranged to cause the DLL circuit to operate at the time of auto-refresh by using the row-active signal RAS.
More specifically, in order to cause the DLL to operate when the device is active and at the time of auto-refresh in the DLL circuit, the row-active signal RAS is utilized as the DLL operation control signal because the nature of the signal RAS is convenient for this purpose. FIG. 22 illustrates the operation of the row-active signal RAS depending upon the status of an SDRAM. Here ACT COM represents an externally applied active command, PRE COM an externally applied precharge command, and AUTO REF COM an externally applied auto-refresh command. The signal RAS in a case where these commands arrive attains the high logic level in active and refresh intervals and the low logic level in a precharge standby state. It is so arranged that when the signal RAS is at the high level, the DLL is caused to operate (DLL ON) by a signal DLL Power Down (DLLPWDN).
If with an increase in the storage capacity of SDRAMs there is an increase in the number of word lines that are refreshed once in the auto-refresh interval, then there will be an increase in peak consumed current. In order to disperse peak current, therefore, it is necessary to stagger or disperse refresh at every specific address or bank. When this is done, the time required for the refresh operation lengthens and hence there is an increase in the auto-refresh interval, which is decided by the JEDEC (Joint Electron Device Engineering Council). For example, the refresh interval lengthens with an increase in storage capacity in the following manner: 75 ns at 256 MB, 105 ns at 512 MB, 127.5 ns at 1 GB, 195 ns at 2 GB, and 327.5 ns at 4 GB.
Conventional control of a DLL at the time of auto-refresh using the signal RAS will now be described in detail. FIG. 23 is a timing chart illustrating a first example of operation of a DLL at the time of refresh according to the related art. Here refresh is performed one time. AUTO REF COM is an externally applied active command. A signal REF is a signal produced within the SDRAM in response to receipt of the auto-refresh command signal AUTO REF COM. At the high level, the signal indicates the refresh interval and the length of the refresh interval is set by a timer so as to fall within tRFC. A signal RAS is a row-active signal and is set in such a manner that the high-level interval of the signal RAS will fall within the high-level interval of the signal REF at refresh time. The interval over which refresh is actually being performed is when the signal RAS is at the high level.
FIG. 24 is a timing chart illustrating a second example of operation of a DLL at the time of refresh according to the related art. Here refresh is performed while being staggered based upon a difference in address. In order to perform refresh in staggered fashion according to a difference in address, use is made of two row-active signals RAS_1 and RAS_2. Here the “i” of signal RAS_i indicates a bank address. The row-active signal RAS is obtained by taking the logical sum of the signals RAS_i the number of which is equivalent to the number of banks (i takes on values of 1 and 2 in FIG. 24).
FIG. 25 is a timing chart illustrating a third example of operation of a DLL at the time of refresh according to the related art. Here refresh is performed while being split based upon a difference in address. In order to split refresh into two refresh segments according to a difference in address, the signal RAS is output while dividing the high interval thereof into two portions (signals RAS_1 and RAS_2).